1. Field of the Invention
The present invention relates to DRAM (Dynamic Random Access Memory) of semiconductor device and method for manufacturing the same, and in particular to an improved DRAM of semiconductor device and method for manufacturing the same wherein a gate insulating film having an ONO (oxide-nitride-oxide) structure is employed to reduce impurity concentrations of a channel region and a well region and improve a leakage current and a refresh characteristics of the device.
2. Description of the Related Art
FIG. 1 is a cross-sectional view illustrating a structure of a conventional DRAM of semiconductor device.
Referring to FIG. 1, the conventional DRAM comprises a device isolation film 20, a deep n-well 15 and a p-well 25 disposed on a semiconductor substrate 10. The conventional DRAM also comprises a stacked structure of a gate oxide film 40 and a gate electrode 45, and a channel region 45 disposed in the semiconductor substrate 10 below the gate electrode 45. A source/drain region 30 is disposed in the semiconductor substrate 10 at both sides of the gate electrode 45.
In the conventional DRAM, a channel length and a channel width decrease as the dimension of the DRAM cell is reduced. The drawbacks of the shrinkage are that a threshold voltage of a cell transistor is decreased and a punch-through phenomenon is easily induced. In order to overcome these problems, a method for increasing impurity concentrations of a channel region and a well region has been proposed.
Generally, the threshold voltage of a cell transistor is defined in Equation 1.
                                                        V              TH                        =                                          Φ                MS                            -                                                Q                  EFF                                                  C                  OX                                            +                              2                ·                                                                        Φ                    F                                                                                -                                                Q                  B                                                  C                  OX                                                              =                                    Φ              MS                        -                                          Q                EFF                                            C                OX                                      +                          2              ·                                                                Φ                  F                                                                      +                          2              ·                                                                                          ɛ                      S                                        ·                    q                    ·                                          N                      A                                        ·                                                                                        Φ                        F                                                                                                                                    C                  OX                                                                    ,                            [                  Equation          ⁢                                          ⁢          1                ]            
where ΦMS is work function difference between the gate electrode and the semiconductor substrate, QEFF is effective charge per unit area of the gate oxide when VG=VTH, COX is capacitance per unit area of the gate oxide, ΦF is Fermi level of the semiconductor substrate, ΦB is charge per unit area of the depletion region, εS is permittivity constant of the semiconductor substrate, q is charge of one electron, and NA is impurity concentration of the semiconductor substrate.
QEFF is defined in Equation 2 below.
                                          Q            EFF                    =                                    Q              SS                        +                          Q                              it                ⁡                                  (                                                            Φ                      S                                        =                                          2                      ·                                              Φ                        F                                                                              )                                                      +                                          ∫                0                                  T                  OX                                            ⁢                                                                    x                    ·                                          ρ                      ⁡                                              (                        x                        )                                                                                                  T                    OX                                                  ·                                                                  ⁢                                  ⅆ                  x                                                                    ,                            [                  Equation          ⁢                                          ⁢          2                ]            
where QSS is surface state fixed charge at the interface between the gate oxide film and the semiconductor substrate, Qit is interface state charge between the gate oxide film and the semiconductor substrate, ΦS is surface potential of the semiconductor substrate, ρ(χ) is oxide charge density within the gate oxide, and TOX is thickness of the gate oxide.
Therefore, the threshold voltage of the cell transistor can be obtained from Equation 3.
                              V          TH                =                              Φ            MS                    -                                    1                              C                OX                                      ⁡                          [                                                Q                  SS                                +                                  Q                                      it                    ⁡                                          (                                                                        Φ                          S                                                =                                                  2                          ·                                                      Φ                            F                                                                                              )                                                                      +                                                      ∫                    0                                          T                      OX                                                        ⁢                                                                                    x                        ·                                                  ρ                          ⁡                                                      (                            x                            )                                                                                                                      T                        OX                                                              ·                                                                                  ⁢                                          ⅆ                      x                                                                                  ]                                +                      2            ·                                                        Φ                F                                                            +                      2            ·                                                                                ɛ                    S                                    ·                  q                  ·                                      N                    A                                    ·                                                                                Φ                      F                                                                                                                      C                OX                                                                        [                  Equation          ⁢                                          ⁢          3                ]            
When the impurity concentrations of a channel region and a well region are increased, NA is increased. As a result, the threshold voltage and the punch-through voltage are increased, thereby overcoming the problems of the conventional art. However, as shown in FIGS. 2a and 2b, the increases in the threshold voltage and the punch-through voltage increase an electric field of a source/drain region, resulting in an increase in a leakage current and degrading a refresh characteristic of the DRAM. Therefore, the proposed method shows its limitation, and a leakage current characteristic and a refresh characteristic are considered when determining a proper impurity concentration.
However, it is very difficult to manufacture a DRAM of semiconductor device wherein the threshold voltage, the punch-through voltage and the refresh characteristic all meet desired level as the dimension of the DRAM is reduced to below 100 nm.
FIG. 3 is a cross-sectional view illustrating a conventional non-volatile memory cell.
Referring to FIG. 3, the conventional non-volatile memory cell comprises a device isolation film 60, a deep n-well 55 and a p-well 65 disposed on a semiconductor substrate 50. The conventional non-volatile memory also comprises a stacked structure of a lower gate oxide film 80 and an intermediate gate nitride film 85, an upper gate oxide film 90 and a gate electrode 95, and a channel region 75 disposed in the semiconductor substrate 50 below the gate electrode 95. A source/drain region 70 is disposed in the semiconductor substrate 50 at both sides of the gate electrode 95.
The conventional non-volatile memory cell stores data by trapping electrons or holes in the intermediate gate nitride film. A threshold voltage changes in case whether electrons or holes are trapped or not. That is, when electrons are trapped in the intermediate gate nitride film, the threshold voltage is increased and when holes are trapped, the threshold voltage is decreased. ‘1’ or ‘0’ can be stored in the non-volatile memory cell using this principle.
For example, when in case of trapping electrons are defined as ‘1’ and trapping holes as ‘0’ (or vice versa), the operation of the non-volatile memory cell is shown in Table 1 below.
TABLE 1GateDrainSourceBulk (p-Operation[V](V)[V]well) [V]ERASEVP000Write ‘1’PROGRAM0VPVPVPWrite ‘0’READVRGVRD00VRG, VRD < VP
During an ERASE operation, VP is applied to the gate electrode and 0V is applied to the drain, the source, the bulk so that the voltage difference between the gate electrode and other contacts is VP(>0), whereby electrons flow from the drain, the source, the bulk into the ONO gate insulating film to be trapped in the ONO gate insulating film. Therefore, the threshold voltage is increased according to Equation 3 and ‘1’ is stored.
During a PROGRAM operation, 0V is applied to the gate electrode and VP is applied to the drain, the source, the bulk so that the voltage difference between the gate electrode and other contacts is −VP(<0), whereby holes flow from the drain, the source, the bulk into the ONO gate insulating film to be trapped in the ONO gate insulating film. Therefore, the threshold voltage is decreased according to Equation 3 and ‘0’ is stored.
During a READ operation, when VRD is applied to the drain, the threshold voltage is greater than VRG in case that ‘1’ is stored and the threshold voltage is smaller than VRG in case that ‘0’ is stored. Therefore, ‘1’ or ‘0’ can be read out when VRG is applied to the gate electrode since the transistor is turned off or on according to the threshold voltage.
In case of a non-volatile memory cell, since the state of the electrons or holes trapped in the intermediate gate nitride film are maintained even when power is cut off, the data can be read out from the transistor when power is again applied to the transistor.
However, a non-volatile memory cell requires a high VP in order to trap electrons or holes during the ERASE or the PROGRAM operation, which is a write operation. Such a write operation also requires 1000 times longer time period compared to the READ operation. Moreover, the amount of electrons or holes trapped in the intermediate gate nitride film decreases as READ or PROGRAM operations are repeatedly performed. Therefore, non-volatile memory cells cannot be used in a DRAM of semiconductor device having frequent read/write operations.
As described above, in accordance with the conventional DRAM of semiconductor device and method for manufacturing the same, wherein a gate insulating film having an ONO (oxide-nitride-oxide) structure is employed to reduce impurity concentrations of a channel region and a well region and improve a leakage current and a refresh characteristics of the device.